(1) Field of the Invention
This invention relates generally to a Low Temperature Polycrystalline Si Thin Film transistor (LTPS-TFT), and more particularly to an LTPS-TFT having a hydrogen-supplying film to enhance hydrogenation.
(2) Description of the Prior Art
Thin film transistor liquid crystal displays (TFT-LCD) as a mature technology, can be categorized into the amorphous Si (α-Si) TFT-LCDs and the Low Temperature Polycrystalline Si (LTPS) TFT-LCDs. The α-Si TFT is a transistor using the amorphous Si as the material for the semiconductor layer. The LTPS-TFT is a transistor using the polycrystalline Si as the material for the semiconductor layer. The LTPS technology features a laser annealing, which can transform the Polycrystalline Si into the α-Si with a temperature lower than 500° C. For the technology of α-Si TFT-LCD is mature and low cost, so it is now the mainstream in the marketplace. However, because the LTPS TFT-LCD has various advantages superior to the α-Si TFT-LCD, so its application becomes one of the prospective technology in the flat panel display industry.
Referring to FIG. 1, a conventional semiconductor device having LTPS-TFTs is shown. In the fabricating process of the semiconductor device 10, first of all, a polycrystalline layer 14 is formed on a substrate 12. After a gate insulator 16 is formed on the polycrystalline layer 14, the polycrystalline layer 14 is performed thereupon an ion implantation to form separately a source 143 and a drain 145 and also to form a channel 141 in a central region of the polycrystalline layer 14. Subsequently, a gate electrode 18 is formed on an upper surface of the gate insulator 16, and is sited above the channel 141. Thereby, a basic MOS structure can be constructed by the gate electrode 18, the gate insulator 16 and the polycrystalline layer 14.
In order to manufacture a driving circuit with an n-MOS and a p-MOS (CMOS) in the LTPS-TFT, the polycrystalline layer 14 can undergo another ion implantation process so as to include predetermined ions for forming respectively the n-MOS and the p-MOS. The gate insulator 16 on the upper surface of the polycrystalline layer 14 provides a thickness to is substantially form a barrier for staying the implanted ions within a predetermined depth of the polycrystalline layer 14 after the ions passing through the gate insulator 16. The latter ion implantation is an ion activation process that can activate the ions at 400-1000° C. so as to make the polycrystalline layer 14 have the function of the semiconductor.
Still referring to FIG. 1, after the gate electrode 18 is formed, an inner layer dielectric (ILD) 22 is deposited on both the gate electrode 18 and the gate insulator 16. Thereafter, the ILD 22 and the gate insulator 16 are etched to form openings for exposing the source 143 and the drain 145, respectively. Then a metal is deposited into aforesaid openings to form the wire 143a on top of the source 143 and the wire 145a on top of the drain 145. Finally, a passivation layer 24 covers on the wire 143a, 145a and the ILD 22 to protect the semiconductor device 10 and so the TFT therein.
One characteristic of the LTPS-TFT is that there is a large number of unsaturated bonds in the polycrystalline Si layer of the LTPS-TFT for the laser annealing process is used. These unsaturated bonds can become charge carrier traps to affect charge moving in the channel 141, and thus further to result in a higher threshold voltage of the LTPS-TFT. In order to improve the current-voltage characteristic and reduce the threshold voltage, a fabricating method is introduced by adding a hydrogenation process to have the unsaturated bonds transformed into respective hydrogen bonds in the channel 141. Thereby, the aforesaid charge carrier traps can be mended and the threshold voltage of the LTPS-TFT can be reduced. The reality is that charge mobility is increased in the channel 141. U.S. Pat. No. 5,162,892 disclosed a polycrystalline Si layer that is 400 Å in thickness. When the polycrystalline Si layer does not undergo a hydrogenation process, its threshold voltage may be 11V and its carrier effective mobility may be 1 cm2/V. But if the polycrystalline Si layer undergoes a hydrogenation process, its threshold voltage would drop to 7V and its carrier effective mobility would be increased to 20 cm2/V.
In an early hydrogenation process, a hydrogen plasma is used to hydrogenate the channel 141. However, the hydrogen plasma may damage the semiconductor device 10 easily and thus to lower the yield. In the latter ion activation process or thermal resistance test, the high-temperature environment may result in escaping of the hydrogen from the polycrystalline layer 10 and may reduce the hydrogenation efficiency. At present, the general hydrogenation method uses the hydrogen-containing material as the passivation layer 24 and performs annealing onto semiconductor device 10. The hydrogen atoms go from the passivation layer 24 into the channel 141 by thermal effusion so as to repair the charge carrier traps. As shown in FIG. 1, the hydrogen atoms go from the passivation layer 24 to the channel 141 along the direction indicated by arrows around the gate electrode 18 in the hydrogenation process. When the semiconductor device 10 runs into the high temperature surroundings again, the hydrogen atoms can be encapsulated in the semiconductor device 10 by the passivation layer 24.
However, the method including forming the passivation layer 24 needs a longer annealing time. Referring to FIG. 1, along the direction indicated by the arrows, the hydrogen atoms can go from the passivation layer 24 down to the interlayer dielectric 22 around the gate electrode 18, then go through the gate insulator 16, and finally go into the channel 141. The aforesaid pathway is too far to achieve a shorter process time. U.S. Pat. No. 5,162,892 discloses that the annealing time and the carrier effective mobility of the TFT are positively correlated. The carrier effective mobility is 1 cm2/V before annealing. After an annealing for 8 hours, the effective mobility can increase to 20 cm2/V.
In view of the aforementioned disadvantages in conventional process, the present inventor has devoted to improving and innovating a method for producing an acceptable semiconductor device and an internal LTPS-TFT.